DRAM (Dynamic Random Access Memory) is a volatile memory.
As for DRAM, data errors often occur during data storage, and thus there is a need for error detection and correction techniques to ensure the correctness of data storage. ECC (Error Correction Code) detects and corrects the erroneous data by adding parity bits to a certain length of data bits. The conventional read and write processes of a DRAM including ECC function are shown in FIG. 1 and FIG. 2 respectively.
FIG. 1 schematically depicts a data write process of a DRAM, in which a data array is used to store data and an ECC array is used to store ECC bits, i.e. parity bits. When an N-bit data is written into a memory from an external source, the N-bit data is used by the memory to generate M-bit parity bits through an ECC encoding circuit. The N-bit data and the M-bit parity bits are temporarily latched, and then written into respective memory arrays by means of write drivers, i.e. the N-bit data is stored in the data array and the M-bit parity bits are stored in the ECC array. The length N of the data is greater than 0 and less than or equal to the length of the data that can be read or written by the memory when the memory performs one read or write operation. The length M of the parity bits is greater than 0 and its value is determined by the selected ECC algorithm. It should be noted that the data array, the ECC array and the ECC encoding circuit are all inside the memory, and the memory may also include other components which are not shown here.
FIG. 2 schematically depicts a data read process of the DRAM. The N-bit data and the M-bit parity bits are read from their respective memory arrays, and temporarily latched after being amplified by the second sense amplifier, and then sent to an ECC error correcting module. The ECC error correcting module can detect and correct errors and output a corrected N-bit data.
It can be known from the data write process shown in FIG. 1 that when the ECC encoding module generates the M-bit parity bits, data bits of length N are required, which is determined by the selected ECC algorithm. However, as for a memory, not all of the input N bits can be used for ECC encoding, that is, the length of the data valid for encoding in the input data is not constant, wherein the data valid for encoding refers to the data that can be used to generate parity bits. For example, the specification of DRAM states that when there is a data-mask or a burst chop mode, several bits in an N-bit input data cannot be used for ECC encoding, and the data length of the data valid for encoding may change, resulting in the data length being less than N. For another example, for structures of different data lengths, such as X4, X8 or X16 mode, etc., the length of the data valid for encoding also changes with external control, resulting in the data length of data valid for encoding being not equal to N. However, once the ECC algorithm has been selected, the data length required by the corresponding ECC encoding module is constant, and thus the ECC bit cannot be successfully generated in the case where the data length of the data valid for encoding changes.
One solution in the prior art is to find a minimum data length within all the constraints that may be encountered, and select an ECC algorithm based on this minimum data length so that all modes can be supported. If the minimum data length is 8, even for the most efficient Hamming code, at least 4 bits of parity bits are required, which increases the memory area by at least 50% so as to store the parity bits of the ECC, resulting in a significant increase in the cost of the memory and a reduction in the flexibility and efficiency of ECC algorithm selection.
If the power consumption of the write operation is not increased, or the timing of the write operation is not affected, or for any other reason the ECC encoding cannot be performed during write operation, the ECC function cannot be realized by the conventional method.
Therefore, there is a need for a new ECC encoding method to solve the above problems.